1. Field of the Invention
The present invention relates to RF (radiofrequency) amplifiers, and more specifically to preamplifiers driving a power amplifier supplying an antenna.
2. Discussion of the Related Art
FIG. 1 illustrates a conventional RF amplification chain 1. The amplification chain includes a signal processing block 2, a preamplifier 3 driving a power amplifier 4 coupled to an antenna 5. Block 2 includes two stages for shaping the signal and mixing the signal with the desired carrier.
As illustrated in FIG. 2, preamplifier 3 may be followed by a switch 6 with two positions, connecting output S of the preamplifier to one of two outputs S1 and S2. In certain applications, it is indeed necessary to interpose two different filters between preamplifier 3 and power amplifier 4 or to supply, with the same preamplifier, two different power amplifiers.
This type of circuit finds an application in fields such as that of cell phones, where the frequency is high, greater than one gigahertz (GHz).
In such fields, some standards use a carrier modulated both in phase and in amplitude. These standards are for example the CDMA (“Code Division Multiple Access”) or the W-CDMA (W standing for “Wideband”). In these fields, RF preamplifiers and amplifiers need to have high performance, needing to be linear both in phase and in amplitude.
In the state of the art, block 2 is an integrated circuit formed on a silicon substrate. Amplifiers 3 and 4 are external units, the active components of which are formed on gallium arsenide substrates. Indeed, gallium arsenide components have a higher cut-off frequency and withstand higher voltages than silicon components.
FIG. 3 illustrates a conventional preamplifier followed by a switching circuit 6. Preamplifier 3, hereafter more simply designated as “the amplifier”, includes an input pad E, coupled to the gate of a transistor TA via an impedance matching circuit 10. Transistor TA is a gallium arsenide transistor of FET type, connected in common source. The gate of transistor TA is biased in direct current by a biasing unit 11, not detailed. The source of transistor TA is coupled to a ground pad 13 (GND) via an inductive resistor L. Pad 13 is connected to ground M of the circuit via a connection wire. This connection wire has, in the considered frequency range (from 1 to a few GHz), a parasitic bonding inductance. The drain of transistor TA is coupled to a supply pad 15 via an impedance matching circuit 14. The connection of pad 15 to a supply line VDD is made by a wire also having a bonding inductance Lb. A capacitor Cgd is shown between the gate and the drain of transistor TA. This capacitor is the stray capacitor between the gate and the drain of transistor TA. The amplifier has its output on the drain of transistor TA.
A switch 6 receives the output of amplifier 3. It has two outputs, S1 and S2. Switch 6 is formed by means of four FET-type gallium arsenide transistors T. The gates of transistors T receive voltages +V or −V via resistors R, and the circuit is formed so that one of the two outputs receives the output signal of the amplifier, while the other one is grounded. The presence of switch 6 in series with the amplifier introduces losses in the processing chain.
The amplifier of FIG. 3 is formed of a single stage. Because of its low adaptability, a two-stage circuit is preferred to it, like that of FIG. 4.
In FIG. 4, the amplifier includes a first stage, similar to the amplifier of FIG. 3. Impedance matching circuit 14 here has an intermediary output enabling driving the second stage of the amplifier. The second stage is formed of a transistor TB, also connected in common source. Transistor TB is also made of gallium arsenide and of FET type. The gate of transistor TB receives the output of the first stage. Its source is connected to a ground pad 17, connected to ground M by a connection having a bonding inductance Lb. Its drain is connected to an output pad S of the amplifier. It is also connected to an impedance matching circuit 18, itself connected to a supply pad 19, connected to a power supply VDD2 via a bonding inductance Lb. If desired, a switch 6 like that of FIG. 3 is connected on output S.
A disadvantage of the amplifier of FIG. 4 is that it includes gallium arsenide transistors, and accordingly, its integration on the integrated circuit of processing block 2, having a silicon substrate, is impossible. Further, the amplifier of FIG. 4 has relatively high power consumption. Also, the structure is sensitive to noise, especially noise introduced by the bonding inductances, which are difficult to evaluate.